In the simplest computer systems, the processor manages the movement of data between the memory and peripheral devices, such as graphics subsystems and ports. Unfortunately, this burdens the processor with not only processing, but moving, all data. As a result, the processor's speed frequently limits the computer's overall performance. More complex computer systems employ direct memory access (DMA). In DMA, a DMA controller separate from the processor moves data between the memory and peripheral devices. The processor's role is therefore reduced, and the computer's overall performance is enhanced.
In computer systems having multiple peripheral devices, each peripheral device is assigned a DMA channel, and allocation (called “granting”) of DMA bandwidth (sometimes expressed in terms of “time slots”) between or among the channels becomes a challenge. In those systems in which the channels are of equal priority, bandwidth is granted based on a round-robin algorithm. In those systems in which the channels are of unequal priority, higher-priority channels are granted bandwidth until they no longer require it. Only then is bandwidth granted to lower-priority channels. The disadvantage of the latter approach is that the lower-priority channels may receive insufficient bandwidth.
One example of the latter approach is found in U.S. Patent Publication 2006/0004931, in which memory access bandwidth within a digital camera is allocated among several channels by assigning each channel a “tokens per snapshot” (TPS) value. Each channel has a DMA engine and a DMA entry queue. If the channel wishes to access the memory, then a DMA entry is pushed onto the DMA entry queue of the channel. An arbiter uses the TPS values to select DMA entries off the various queues for incorporation into a “snapshot.” The arbiter then selects DMA entries from the snapshot in an order for servicing such that memory access overhead in accessing the memory is reduced. Only after all DMA entries of the snapshot have been serviced is another snapshot of entries selected. Maximum latency in servicing a queue is controlled by assigning each queue a time-out value (TOV). If a queue times out, then that queue is moved up in the order of servicing.
In U.S. Pat. No. 6,430,194, bus access is arbitrated among modules connected to a common bus. Each module has a priority level and an arbitration number assigned to it. More than one module can have the same priority level. For each priority level, the arbitration numbers assigned are unique. When two or more modules attempt bus access at the same time, the one with the higher priority level wins access. If the priority levels are the same but one module has already accessed the bus, the module that has been waiting wins access. If the modules have the same priority level and have been waiting then the module with the highest arbitration number wins access.
U.S. Pat. No. 7,085,875 discloses a modular switch, comprising a plurality of backplane sub-buses; a plurality of cards which are each allocated one or more of the backplane sub-buses and a controller that dynamically allocates the backplane sub-buses to the plurality of cards, based on the bandwidth needs of the cards. Preferably, the bandwidth capacity of substantially all the backplane sub-buses is less than the sum of the maximal transmission bandwidth capacities of the cards.
In U.S. Pat. No. 7,360,068, a dynamically reconfigurable processing unit includes a microprocessor and an embedded flash memory for nonvolatile storage of code, data and bitstreams. The embedded flash memory includes a field programmable gate array (FPGA) port. The reconfigurable processing unit further includes a direct memory access (DMA) channel, and an SRAM embedded FPGA for FPGA reconfigurations. The SRAM embedded FPGA has an FPGA programming interface connected to the FPGA port of the flash memory through the DMA channel interface.
PCT Application No. WO/2002/039631 discloses a method of prioritizing network resources in a network that includes providing the network with a high priority channel and a low priority channel. The high priority channel has insufficient bandwidth resources to transmit a message on the high priority channel. The high priority channel reserves bandwidth resources from a local free list. If this is insufficient, the high priority channel preempts bandwidth resources of the low priority channel. If this is insufficient to send the message, the high priority channel obtains bandwidth resources from the nodes in the network so the message can be send on the high priority channel.